Amr Lotfy


Full Name:
Amr Lotfy
Current Position: SOC Design Engineer at Intel Corporation (Clocking Mixed Signal Validation and Design   Modeling Team Lead).

Address: Hillsboro, Oregon, USA
Mobile: 001 9712587723
Email: amr.m.lotfy@gmail.com

 


Education background:
[B.Sc.] Electrical Engineering, Alexandria University
[M.Sc.] Microelectronic System Design, Nile University

Research Interest:
Digital Phase Locked Loops
Clocking Schemes for Microprocessors and High-Speed Links

Thesis Title:
A TDC-Based All Digital PLL With Non-Linear Characteristics And Sub-Micron Lock Time

Date of Defense: December 2011

Supervisors:
Dr. Maged Ghoneima
Dr. Rafik Guindi
Dr. Mohamed Abdel-Moneum


Conference papers:

  • A. Lotfy, S. Farooq, Q. Wang, S. Yaldiz, P. Mosalikanti, N. Kurd “A System Verilog Behavioral Model for PLLs for Pre-Silicon Validation and Top-Down Design Methodology” IEEE Custom Integrated Circuits Conf. (CICC), Sep. 2015.
  • A. Lotfy, M. Ghoneima, and M. Abdel-Moneum “A Novel Power Gated Digitally Controlled Oscillator” International Conference on Energy Aware Computing (ICEAC), Nov. 2011.
  • M. Abdelsalam, M. Abdelmejeed, A. Lotfy, M. Abdel-Moneum, N. Kurd, and G. Taylor “Digital Adaptive Frequency Scaling in All Digital Phase Locked Loop with Digital Built In Self Test”. DTTC 2013 (Intel Internal Conference).
  • Safwat, A. Lotfy, M. Ghoneima, and Y. Ismail “A 5-10GHz Low Power Bang-Bang All Digital PLL Based on Digital Loop Filter Programmable Coefficients” IEEE Int. Symp. Circuits and Systems (ISCAS), May. 2012.
  • Abdelfattah, M. Ghoneima, and Y. Ismail, A. Lotfy, M. Abdel-moneum, N. Kurd, G. Taylor “ Modeling the Response of Bang-Bang Digital PLLs to Phase Error Perturbations”. IEEE Custom Integrated Circuits Conf. (CICC), Sep. 2012.
  • Abdelfattah, M. Ghoneima, and Y. Ismail, A. Lotfy, M. Abdel-moneum, N. Kurd, G. Taylor “ A Novel Digital Loop Filter Architecture for Bang-Bang ADPLL”. IEEE International System-on-Chip Conference, (SOCC), Sep 2012.
  • Kurd, M. Abdelmoneum, A. Lotfy, M. Abdelsalam, M. Abd-El Mejeed, G. Taylor, “Scalable True All Digital PLL Architectures”, 2013 Tech Fest, ICTC, Analog and IO, San Antonio Texas, Jan. 24-27, 2013.

Patents:

  • A. Lotfy, M. Abdelsalam, M. Abdelmejeed, N. Kurd, M. Abdel-moneum, M. Elzinga, Y. M. Park, J. R. Rapeta, and S. Musunuri “Apparatus and Method for Fast Phase Locking for Digital Phase Locked Loop”. US Patent Pending, Intel Corporation, Filed September 2013, Filing Number: PCT/US2013/061997.
  • Abdel-Moneum, ­N. Kurd, A. Lotfy, M. Abdelsalam, and M. Abdelmejeed “Apparatus for Dynamically Adapting a Clock Generator With Respect to Changes in Power Supply”. US Patent Pending, Intel Corporation, Filed March 2013, Application Number: 13/789,241.
  • A. Lotfy, M. Abdelsalam, M. Wahba, N. Kurd, and M. Abdel-Moneurm “Apparatus and System for Digitally Controlled Oscillator”. US Patent, Intel Corporation, Published Sep 2013, Publication Number: WO2013141863 A1.

Other Activities:

  • Technical Reviewer for the IEEE-TCAS-I and TVLSI journals.
  • Reading, Tennis, Soccer, Basketball.