Hossam Sarhan


Full Name:
Hossam Sarhan
Current Position: PhD researcher at CEA-Leti, Grenoble, France.

Address: Grenoble, France
Mobile: 0033 785599033
Email: hossam.sarhan@ieee.org

 


Education background:
[B.Sc.] Electrical Engineering, Alexandria University
[M.Sc.] Microelectronic System Design, Nile University
[PhD] Electronics System Design (EEATS), University of Grenoble (INPG), France.

Research Interest:
3D Integrated Circuits
On-chip voltage regulators
High-performance/low-power digital design
Analytical modeling for complex circuits.

Thesis Title:
Optimized Crossbar For 3D Memory-Centric Network-on-Chip (3D McNoC)

Date of Defense: September 2011

Supervisors:
Dr. Amr Wassal
Dr. Rafik Guindi


 

Conference papers:

  • Sarhan, S. Thuries, O. Billoint, F. Clermidy, “A Power-Performance Study For Monolithic 3D Integrated Circuit Design Using Un-Balanced Area Ratio Approach”, Design Automation Conference (DAC), Work in Progress (WIP) session, 2015.
  • Sarhan, S. Thuries, O. Billoint, F. Depart, P. Batude, F. Clermidy, “Intermediate BEOL process influence on Power and Performance For 3DVLSI”, 3D System Integration, 2015. (3DIC). IEEE International Conference on. IEEE, 2015.
  • Sarhan, S. Thuries, O. Billoint, F. Clermidy, “An Un-Balanced Area Ratio Study for High Performance Monolithic 3D In
  • Sarhan, S. Thuries, O. Billoint, F. Clermidy, “3DCoB: A new design approach for Monolithic 3D Integrated Circuits”, Asia and South Pacific Design Automation Conference (ASP-DAC), IEEE, 2014.
  • tegrated Circuits”, ISVLSI, IEEE Computer Society Annual Symposium on. (ISVLSI), 2015.
  • Billoint, H. Sarhan, Iyad Rayane, M. Vinet, P. Batude, et al., “A Comprehensive Study of Monolithic 3D Cell on Cell Design Using Commercial 2D Tool”, Design Automation and Test in Europe (DATE), 2015.
  • B. Boguslawski, H. Sarhan, F. Heitzmann, F. Seguin, S. Thuries, O. Billoint, F. Clermidy, “Compact Interconnect Approach for Networks of Neural Cliques Using 3D Technology”, Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2015.
  • Billoint, H. Sarhan, Iyad Rayane, M. Vinet, P. Batude, et al., “From 2D to Monolithic 3D: Design Possibilities, Expectations and Challenges” Proceedings of the 2015 Symposium on International Symposium on Physical Design, (ISPD) ACM, 2015.
  • Sarhan and Amr Wassal. “Optimization of TSV-based Crossbars for a 3D Memory-Centric Network-on-Chip.”, The 19th International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA), 2013.
  • Wassal, H. Sarhan, A. ElSherief, “Novel 3D Memory-Centric NoC Architecture for Transaction-Based SoC Applications”, IEEE Proceedings of the Saudi International Electronics, Communications and Photonics Conference (SIECPC), Apr. 2011.
  • H. Sarhan, O.K.Eddash, M. Raymond, A. Wassal, Y. Ismail, “Temperature-Aware Adaptive Task-Mapping Targeting Uniform Thermal Distribution in MPSoC Platforms”, International Conference of Energy Aware Computing (ICEAC), IEEE 2010.

Patents:

  • Hossam SARHAN, Olivier BILLOINT, Fabien CLERMIDY, Sébastien THURIES. 2014. 3D circuit design method. FRANCE. N° E.N.: 14 60962. Filing date 13/11/2014.

Other Activities:

  • A technical reviewer in IEEE Transaction on Circuits and Systems (TCAS-I)
  • Reading, travel and photography: www.500px.com/hossamsarhan