A new clock distribution technique is introduced in this paper. The technique avoids repeaters completely and distributes the clock directly on the passive interconnect network. The wires can be highly lossy, yet the clock is delivered with a very good shape and eye. The technique uses the characteristics of the interconnect to attenuate all frequency components equally. The resulting clock at the

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A major portion of the power consumed in today's systems is due to the clock distribution network. Solutions attempted to reduce clocking power result in low efficiency systems or systems with high complexity control schemes. In this work, a low power clock generator is introduced that can reduce switching power of the clock by almost 75%. This circuit uses the charge recycling concept to achieve

Multi-core and many-core Systems-on-Chip (SoC) are growing more complex than ever. Consequently, developing system models for such SoCs to guide and validate architectural and implementation decisions is becoming a daunting task. It consumes a huge amount of time and effort just to get the model up and running. Although these system models can be fairly abstracted, they still require the setup of

Convolutional codes are one of the Forward Error Correction (FEC) codes that are used in every robust digital communication system. Viterbi algorithm is employed in wireless communications to decode the convolutional codes. Such decoders are complex and dissipate large amount of power. Software Defined Radio (SDR) is realized using highly configurable hardware platforms. Field Programmable Gate

Field Programmable Gate Array technology (FPGA) is a highly configurable option for implementing many sophisticated signal processing tasks in Software Defined Radios (SDRs). Those types of radios are realized using highly configurable hardware platforms. Convolutional codes are used in every robust digital communication system and Viterbi algorithm is employed in wireless communications to decode