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On the Design Flow of the Fractional-Order Analog Filters Between FPAA Implementation and Circuit Realization
This work explicitly states the design flows of the fractional-order analog filters used by researchers throughout the literature. Two main flows are studied: the FPAA implementation and the circuit realization. Partial-fraction expansion representation is used to prepare the approximated fractional-order response for implementation on FPAA. The generalization of the second-order active RC analog filters based on opamp from the integer-order domain to the fractional-order domain is presented. The generalization is studied from both mathematical and circuit realization points of view. It is
FPGA Implementation of Reconfigurable CORDIC Algorithm and a Memristive Chaotic System with Transcendental Nonlinearities
Coordinate Rotation Digital Computer (CORDIC) is a robust iterative algorithm that computes many transcendental mathematical functions. This paper proposes a reconfigurable CORDIC hardware design and FPGA realization that includes all possible configurations of the CORDIC algorithm. The proposed architecture is introduced in two approaches: multiplier-less and single multiplier approaches, each with its advantages. Compared to recent related works, the proposed implementation overpasses them in the included number of configurations. Additionally, it demonstrates efficient hardware utilization
On the fractional order generalized discrete maps
Chaos theory describes the dynamical systems which exhibit unpredictable, yet deterministic, behavior. Chaotic systems have a remarkable importance in both modeling and information processing in many fields. Fractional calculus has also become a powerful tool in describing the dynamics of complex systems such as fractional order (FO) chaotic systems. The FO parameter adds extra degrees of freedom which increases the design flexibility and adds more control on the design. The extra parameters increase the chaotic range. This chapter provides a review of several generalized discrete time one
On the Approximation of Fractional-Order Circuit Design
Despite the complex nature of fractional calculus, it is still fairly possible to reduce this complexity by using integer-order approximation. Each integer-order approximation has its own trade-offs from the complexity, sensitivity, and accuracy points of view. In this chapter, two different fractional-order electronic circuits are studied: the Wien oscillator and the CCII-based KHN filter with two different fractional elements of orders α and β. The investigation is concerned with changes in the response of these two circuits under two approximations: Oustaloup and Matsuda. A detailed review
A Unified System for Encryption and Multi-Secret Image Sharing Using S-box and CRT
Multi-Secret Image Sharing (MSIS) is used when multiple images need to be shared to multiple participants, but the images can not be recovered without the presence of all shares. In this paper, a unified system for performing encryption and (n,n)-MSIS is proposed. While MSIS is based on the XOR operation, encryption combines the utilization of Chinese Remainder Theorem (CRT), SHA-256, and S-box for improved security. The same designed system is used for the generation of secret shares and the recovery of secret images. In addition, a sensitive system key is designed where three pairwise
Fractional-Order Filter Design
One of the advantages of fractional order is the extra degree of freedom added by the fractional-order parameters, which enrich the analysis with more details in new dimensions. This chapter introduces factional-order conventional filters of orders α, 2α, and 3α. The general transfer functions of continuous-time filters (low-pass, high-pass, and band-pass filters) to the noninteger-order (fractional-order) domain are investigated. Also, mathematical expressions for the maximum and minimum frequencies, the half power frequencies, and the right-phase frequencies are derived. In addition, the
FPGA realization of fractals based on a new generalized complex logistic map
This paper introduces a new generalized complex logistic map and the FPGA realization of a corresponding fractal generation application. The chaotic properties of the proposed map are studied through the stability conditions, bifurcation behavior and maximum Lyapunov exponent (MLE). A relation between the mathematical analysis and fractal behavior is demonstrated, which enables formulating the fractal limits. A compact fractal generation process is presented, which results in designing and implementing an optimized hardware architecture. An efficient FPGA implementation of the fractal behavior
Design and fabrication of CNT/graphene-based polymer nanocomposite applications in nanosensors
Development and improvement of nanosensors have been active research areas over the last few decades. Many materials and compounds have been investigated for their sensing properties. This work is concerned with developing a new sensing layer for gas sensors based on chitosan as a polymer enhanced with graphene as a nanofiller. The graphene used for preparing the chitosan solution was at 0.1, 0.5, and 1 wt%. Many characterizations (such as using different pore size, gas permeability, mechanical properties, and electrical resistance) were tested to give full insight into the nanocomposite
Extended RC Impedance and Relaxation Models for Dissipative Electrochemical Capacitors
Electrochemical capacitors are a class of energy devices in which complex mechanisms of accumulation and dissipation of electric energy take place when connected to a charging or discharging power system. Reliably modeling their frequency-domain and time-domain behaviors is crucial for their proper design and integration in engineering applications, knowing that electrochemical capacitors in general exhibit anomalous tendency that cannot be adequately captured with the traditional RC-based models. In this study, we first review some of the widely used fractional-order models for the
DT2CAM: A Decision Tree to Content Addressable Memory Framework
Decision trees are powerful tools for data classification. Accelerating the decision tree search is crucial for on-the-edge applications with limited power and latency budget. In this article, we propose a content-addressable memory compiler for decision tree inference acceleration. We propose a novel 'adaptive-precision' scheme that results in a compact implementation and enables an efficient bijective mapping to ternary content addressable memories while maintaining high inference accuracies. We also develop a resistive-based functional synthesizer to map the decision tree to resistive
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