In this short communication we analyze the impact of signal harmonics on the formation of the pinched hysteresis loop using a commercial memristor device. We show that by using only the fundamental frequency and the second harmonic components, extracted from the measured electrical current signal, a distortion-less pinched hysteresis loop is re-created. This loop is then used to simulate memristor

In this paper, a CMOS wide-band low-power second-order voltage-mode allpass filter design is proposed as a true time delay element. The proposed allpass filter core design consists of a single transistor, three resistors, one capacitor and one inductor. As a time delay element, the proposed circuit exhibits a group delay of 34 ps within a bandwidth of 8 GHz while consuming only 926 μW from a 1-V

Pinched hysteresis behavior is considered evidence of the existence of the memristive element. Recently, the multi-lobes (more than two) behavior has been discovered in some memristive devices. In this paper, a fractional-order flux/voltage-controlled memristive model is introduced that is able to develop multiple symmetric and asymmetric pinch-off points. Generalized closed-form expressions for

In this paper, the application of the theory of Lissajous figures to the creation of pinched hysteresis loops, considered to be a characteristic of memristive systems, is demonstrated and experimentally verified using designed electronic circuits in the form of an input impedance. The relationship between the Lissajous-based model of the pinched hysteresis loop and a previously reported integrator

This paper presents two CMOS designs of a second-order voltage-mode allpass filters (APFs) for high-frequency applications. Each of the proposed filters is based only on a single transistor and four surrounding impedances. The first proposed allpass filter is an RL filter while the second proposed one is an RLC filter. A detailed analysis along with the parasitic effects is provided for each of

This paper proposes a general prototype fractional order filter based on a two-port network concept with four external impedances. Three induced classifications from the general prototype are extracted with one, two and three external impedances, achieving ten possible generalized topologies. The external impedances are fractional-order elements and resistors. There are forty-six filters divided

Exploring the implementation of fractional calculus is essential to be adequately used in several applications. This paper introduces an FPGA design methodology of fractional order multi-scrolls chaotic system. Hardware resources comparison proves the efficiency of the proposed method. The designs are simulated using Xilinx ISE 14.7 and realized on FPGA Xilinx Artix 7. Different interesting

Due to the non-linear relation between current and voltage of the PV modules, DC/DC power electronic converters are used to adapt this non-linearity. Controllers are used to control the DC/DC converters in order that, they can take actions against changes in irradiance input levels, temperature input levels and load values. In this study, a standalone PV system that feeds a DC load is simulated

This paper proposes the realization of grounded and floating fractional order mem-elements (FOMEs) based on two- and three-port mutators, respectively. Three different topologies based on two-port mutators are implemented using the four members of the second-generation current conveyor (CCII) family which is useful to achieve several realizations for the same circuit. The Fractional Order Mem

A novel topology for simultaneous emulation of fractional-order capacitors and inductors is presented in this paper. In particular, only one control terminal is used in order to select the type of the element as well as its fractional order. This is achieved through an appropriate fitting of the expressions of the intermediate bias currents, in such a way that, eventually, only the adjustment of