As the usage of very large scale integration (VLSI) in computers continues to increase, debugging of timing problems on actual hardware becomes more and more difficult. The post-layout gate-level simulation constitutes a critical design step for timing closure. The major drawback of traditional post-layout gate-level simulation is its long analysis time, which increases as design complexity

Recently, conventional logistic maps have been used in different vital applications like modeling and security. However, unfortunately the conventional logistic maps can tolerate only one changeable parameter. In this paper, three different generalized logistic maps are introduced with arbitrary powers which can be reduced to the conventional logistic map. The added parameter (arbitrary power)

This paper presents a general synchronization technique and an amplitude modulation of chaotic generators. Conventional synchronization and antisynchronization are considered a very narrow subset from the proposed technique where the scale between the output response and the input response can be controlled via control functions and this scale may be either constant (positive, negative) or time

This paper presents a general procedure to obtain Butterworth filter specifications in the fractional-order domain where an infinite number of relationships could be obtained due to the extra independent fractional-order parameters which increase the filter degrees-of-freedom. The necessary and sufficient condition for achieving fractional-order Butterworth filter with a specific cutoff frequency

Recently, Memristive elements such as memristor, memcapacitor and meminductors have become very attractive components in many applications, due to its unique behavior which can not be obtained using the other conventional elements. This paper discusses the analytical analysis of two memcapacitors connected in series and in parallel taking the effect of mismatch in mobility factor and polarity of

This paper introduces a new architecture that improves the throughput of the two-stage Time to Digital Converter (TDC). An oscillator-based TDC is used for conversion. The time residue from the first stage is generated directly after the stop signal is asserted and saved in the form of phase-shift between two oscillating signals. Instead of using two stages, an asynchronous control block is

An ultra low power wake-up receiver for Wireless Sensor Network (WSN) applications is presented. The proposed wake-up receiver is composed of two stages. The first stage is a low-power low-sensitivity stage that acts as a 'sentinel' and continuously monitors the channel, while the second stage is a conventional low-power wake-up receiver. The 2.44GHz two-stage receiver has a sensitivity of -72dBm

This paper presents a generalized post-processing technique for enhancing the pseudorandomness of digital chaotic oscillators through a nonlinear XOR-based operation with rotation and feedback. The technique allows full utilization of the chaotic output as pseudorandom number generators and improves throughput without a significant area penalty. Digital design of a third-order chaotic system with

This paper introduces the modified single input Op-Amps memristor based oscillator. The oscillator is realized with ideal, LM741 and current feedback (AD844) Op-Amps where memristors replace resistors. The effect of memristor on the oscillation frequency and the oscillation condition that are totally independent is studied. This helped in studying the whole operation regime of the memristor. The

This paper presents a new technique to reduce the conversion time, hence improve the throughput, of the two-stage Time to Digital Converter (TDC) architecture. An oscillator based TDC is used in the first and second stages. The time residue from the first stage is generated directly after the stop signal is asserted and saved in the form of phase-shift between two oscillating signals. A throughput