This paper presents the design and the implementation of a low power bang-bang all digital phase locked loop (BBADPLL). The design of the proposed architecture is based on the programmable coefficients of the digital loop filter (DLF) that manages the tradeoffs between stability and jitter of a closed loop. A proposed simple digital controlled oscillator (DCO) based on three stages ring oscillator

This paper presents a modified design for a self-timed SerDes transceiver that was recently published [1]. The new architecture overcomes the main problems that arise in [1], while offering the same advantages. Resistive termination is used instead of source matching to eliminate the need for Manchester coding in [1], this resistive termination increased the data rate to be 16Gbps compared to

Analysis and optimization of switched-capacitor (SC) dc-dc converters with a series inductive filter are developed. The steady-state output impedance of such SC resonant converters is calculated for a 21 conversion ratio. In addition, the necessary conditions for proper application of the output inductive filter are derived. The proposed optimization methodology applies numerical optimization to

Resonant clocking is a promising low power alternative for conventional clocking method. In this work, a design methodology is presented for square wave resonant clocking technique to assure minimum power consumption. These equations were verified by designing a differential clock generator which showed 55% power savings compared to conventional clocking. © 2012 IEEE.

This paper presents a new image encryption scheme based on the fractional-order Lorenz system which gives more degrees of freedom in key generation. In the modified fractional-order system, the key length is doubled using the three fractional-orde r parameters beside the three initial conditions, which makes it invulnerable to brute-force attacks. In addition, using a very simple algorithm, based

Power reduction is the main challenge facing circuit designers in their quest to utilize the full performance of new process technologies. A major portion of the power consumed in today's systems is due to the clock generation and distribution. Resonant clocking has been a promising technique to reduce the clock power dramatically. In this paper, a novel resonant clock generator circuit is

A process and temperature variation calibration scheme is proposed in this paper. The proposed system uses the supply voltage and body bias to calibrate the device parameters to match those of a certain process corner that is determined by the system designer. This scheme is characterized by its ability to dynamically change the desired mapping target according to the computational load. Moreover

A novel ripple mitigation technique is proposed for switched-capacitor voltage regulators (SCVR), which eliminates the output voltage ripple without using multi-phase interleaving. An inner control loop matches the SCVR's switch current to the load current on a cycle by cycle basis. A 2-phase 32 SCVR is designed in 45-nm CMOS process with the proposed control. For a 1.8 V to 1.05 V /40 mA

Large and complex system-on-chip devices consisting of many processor cores, accelerators, DSP functions and many other processing and memory elements are becoming common in the semiconductor industry nowadays. To communicate, these processing and memory elements need to have a network-on-chip (NoC) that is scalable enough to support large number of elements and large bandwidth among other

In this paper a novel power gated digitally controlled oscillator (DCO) is presented. The DCO is suitable for integration in various systems such as clock generation circuits, clock and data recovery, and clocking schemes for high speed links. Simulations of the proposed DCO on 65nm TSMC technology show frequency range of 2.5 GHz to 6.8 GHz across all corners. The proposed DCO consumes only 1.7 mW