A novel technique to remove the slow-switching-limit (SSL) loss in switched-capacitor (SC) dc-dc converters is presented. A small series inductor is cascaded with an SC converter causing adiabatic charging of the converter's energy-transfer capacitors. In this work, the theory and necessary conditions for SSL loss elimination through an inductive output filter are derived. The new topology enables

In this paper, a new self-timed signaling technique for reliable low-power on-chip SerDes (Serialization and DeSerialization) links is presented. The transmitter serializes 8 parallel bits at 1.5GHz, and multiplexes the 12Gbps serial data stream with a 24GHz clock on a single line using three level signaling. This new signaling technique enables the receiver to recover the clock from the data with

In this paper, a power-aware process variation calibration scheme is proposed. The proposed calibration system provides the ability to detect and control the n- and p-type variations independently through the use of all-n and all-p ring oscillators. Calibration is then carried out through the use of the supply voltage and body bias to alter the device parameters to match those of a certain process

A novel low dropout (LDO) voltage regulator compensation technique is demonstrated. A parallel feedback path is used to insert a zero at approximately three times the output pole. The parallel feedback consists of passive elements only and occupies small area. The proposed technique completely eliminates the output pole at different load conditions and results in high LDO bandwidth, which achieves

This paper represents a new self timed signaling technique for low power SerDes transceiver. A three level coding technique enables extracting the clock from the data using simple phase detector rather than using complex power hungry blocks such as Clock Data Recovery (CDR) or a Phase Locked Loop (PLL). This SerDes transceiver was implemented using 90nm TSMC technology. The transmitter serializes

A novel double-bound hysteretic regulation scheme to control multi-phase interleaved Switched-Capacitor DC-DC converters is presented. The control scheme adjusts the number of interleaved phases with the SC converter's switching frequency to significantly reduce the required operating frequency of the control comparator, enabling the practical application of hysteretic control with large number of

As on-chip integration increases, the thermal distribution becomes spatially non-uniform and varies based on the power dissipation. In this paper, we introduce a temperature-aware task-mapping algorithm to prevent hotspots and achieve a highly uniform thermal distribution using adaptive multi-threshold values. The algorithm monitors the temperature of the cores, swaps tasks when the temperature of

To understand the physical process involved in film evaporation, a new numerical model is created using coupled quadratic finite element formulation of the conservation equations. The heat transport equation is solved in the three different phases (solid, liquid and vapor) while the Navier-Stokes equation are solved in the two fluids. The gradient discontinuity at the liquid vapor interface

A simple temperature sensor in Bi-CMOS technology is proposed for applications with low frequency temperature variations in addition to a complete analysis of each block in the system. Most CMOS temperature sensors are based on the temperature characteristics of parasitic bipolar transistors. Two important factors need to be met in the design of the sensor: the first is the accuracy of the sensor

A novel digital comparator topology is presented. The proposed digital comparator cell uses transistors' ratio to program a fixed comparison level. A double-bound hysteretic control comparator, for DC-DC converters, is built using the proposed digital comparator cell. The hysteretic-band width variation, due to process effects, decreases with increased preamplifier stage gain and constitutes a