The coming years may see the advent of distributed implantable devices to support bioelectronic medicinal treatments. Communication between implantable components and between deep implants and the outside world can be challenging. Percutaneous wired connectivity is undesirable and both radiofrequency and optical methods are limited by tissue absorption and power safety limits. As such, there is a

This paper proposes digital design and realization on Field-Programmable Gate Array (FPGA) of the Fractional-order (FO) delayed financial chaotic system. The system is solved numerically using the approximated Grünwald-Letnikov (GL) method. For the purpose of FPGA realization, the short memory principle and an approximate GL with limited window size are utilized. Lookup Tables (LUTs) are employed

The constant phase element (CPE) or fractional-order capacitor is an electrical device that has an impedance of the form Z(s)=1/Cαsα, where Cα is the CPE parameter and α is a fractional dispersion coefficient of values between 0 and 1. Here we show that in the time-domain the classical linear charge-voltage relationship of ideal capacitors, q=C·v, is not valid for CPEs. In fact the relationship is

Wireless power transfer (WPT) has been widely employed in many applications. Its advantages have added more safety and ease in various medical, industrial, and electrical applications. This paper investigates the two-port network concept in the analysis of the fractional-Order WPT circuit. A general expression for the WPT efficiency as a function of two-port network parameters is derived. It is

The low-frequency impedance hook in perovskite solar cells (PSC) is a feature that has been frequently associated with the behavior of passive circuits of inductors or negative capacitances. However, if the experimental impedance data do not transform according to the Kramers-Kronig (KK) relations, the system does not fulfill the conditions of linearity, stability, causality and finiteness

This paper presents a novel lossless image encryption algorithm based on edge detection and generalized chaotic maps for key generation. Generalized chaotic maps, including the fractional-order, the delayed, and the Double-Humped logistic maps, are used to design the pseudo-random number key generator. The generalization parameters add extra degrees of freedom to the system and increase the

Nowadays, the interconnect circuits' conduct plays a crucial role in determining the performance of the CMOS systems, especially those related to nano-scale technology. Modeling the effect of such an influential component has been widely studied from many perspectives. In this article, we propose a new general formula for RLC interconnect circuit model in CMOS technology using the fractional-order

This paper introduces a new representation of the human brain neuron cell response. Implementation of a single cell model of an excitatory and inhibitory neuron. The architecture is based on mimic the real reaction of the neuron cell. Excitatory and inhibitory are implemented in generic form for all neuron's behavior. The design is tested experimentally using FPGA. The designs have been realized

The paper proposes voltage-controlled first-and second-order memristor emulators. The emulators are designed using an operational-transconductance amplifier (OTA) and voltage multiplier blocks plus a fractional-order capacitor. The presented second-order emulator provides two pinched points controlled by order of the employed fractional-order capacitor. Numerical and PSPICE simulation results

This work introduces a new successive approximation register circuit (SAR) for SAR analog to digital converter (ADC) based on Dynamic Random Access Memory (DRAM) cells. Based on the proposed DRAM based SAR ADC and a differential capacitive DAC, a 10-bit 2V ADC is designed in 0.18um CMOS technology. The proposed SAR is compared to traditional SAR to verify that the proposed SAR decreases the power