Implantable probes with built-in light emitters have a promising potential for a range of applications, in particular optogenetic neural stimulation. However, where soft encapsulation methods are used, lifetime will be a function of the quality of encapsulation and the driving mechanism. We have found that a balanced driving mechanism - whereby the integral voltage on encapsulated contacts, can

This work introduces a new successive approximation register circuit (SAR) for SAR analog to digital converter (ADC) based on Dynamic Random Access Memory (DRAM) cells. Based on the proposed DRAM based SAR ADC and a differential capacitive DAC, a 10-bit 2V ADC is designed in 0.18um CMOS technology. The proposed SAR is compared to traditional SAR to verify that the proposed SAR decreases the power

This paper introduces a new representation of the human brain neuron cell response. Implementation of a single cell model of an excitatory and inhibitory neuron. The architecture is based on mimic the real reaction of the neuron cell. Excitatory and inhibitory are implemented in generic form for all neuron's behavior. The design is tested experimentally using FPGA. The designs have been realized

The paper proposes voltage-controlled first-and second-order memristor emulators. The emulators are designed using an operational-transconductance amplifier (OTA) and voltage multiplier blocks plus a fractional-order capacitor. The presented second-order emulator provides two pinched points controlled by order of the employed fractional-order capacitor. Numerical and PSPICE simulation results

Nowadays, the interconnect circuits' conduct plays a crucial role in determining the performance of the CMOS systems, especially those related to nano-scale technology. Modeling the effect of such an influential component has been widely studied from many perspectives. In this article, we propose a new general formula for RLC interconnect circuit model in CMOS technology using the fractional-order

Multi-level electronic systems offer speed and area simplicity, reducing the complexity of implementation and power dissipation. In this paper, a Hybrid ternary Full Adder (FA) is proposed using Conventional Complementary Metal Oxide Semiconductor (CCMOS), Double Pass-transistor Logic (DPL), and Pass Transistors (PT). The proposed FA is extended up to 64-bits to test scalability. To validate the

Due to the good correlation between the physiological and pathological conditions of fruits and vegetables and their equivalent Cole impedance model parameters, an accurate and reliable technique for their identification is sought by many researchers since the introduction of the model in early 1940s. The nonlinear least squares (NLS) and its variants are examples of the conventional optimization

In this work, a generic impedance modeling technique is proposed. The technique is able to identify a circuit model that is most suitable for fitting measured impedance magnitude data using a genetic algorithm solver as well as the optimum circuit model parameters. Experimentally measured and simulated data sets with different noise levels are used to validate the technique. © 2020 Elsevier GmbH

This paper introduces a fractional-order eardrum Type-II model, which is derived using fractional calculus to reduce the number of elements compared to its integer-order counterpart. The proposed fractional-order model parameters are extracted and compared using five meta-heuristic optimization techniques. The CMOS implementation of the model is performed using the Design Kit of the Austria Mikro

The basic idea behind fractional calculus is that it considers derivatives and integrals of non-integer orders giving extra degrees of freedom and tuning knobs for modeling complex and memory dependent systems with compact descriptions. This paper reviews fractional calculus history, theory, and its applications in electrical engineering. The basic definitions of fractional calculus are presented