This paper introduces a new representation of the human brain neuron cell response. Implementation of a single cell model of an excitatory and inhibitory neuron. The architecture is based on mimic the real reaction of the neuron cell. Excitatory and inhibitory are implemented in generic form for all neuron's behavior. The design is tested experimentally using FPGA. The designs have been realized

This work introduces a new successive approximation register circuit (SAR) for SAR analog to digital converter (ADC) based on Dynamic Random Access Memory (DRAM) cells. Based on the proposed DRAM based SAR ADC and a differential capacitive DAC, a 10-bit 2V ADC is designed in 0.18um CMOS technology. The proposed SAR is compared to traditional SAR to verify that the proposed SAR decreases the power

Implantable probes with built-in light emitters have a promising potential for a range of applications, in particular optogenetic neural stimulation. However, where soft encapsulation methods are used, lifetime will be a function of the quality of encapsulation and the driving mechanism. We have found that a balanced driving mechanism - whereby the integral voltage on encapsulated contacts, can

The paper aims to propose three different inverse memristor emulators based on serveral active blocks. One of the presented emulator realizes employing second generation current conveyor (CCII) andcanalog voltage multiplier with passive elements. The other two introduced emulators are designed using cureent feedback operational amplifier (CFOA) with two switches or two BJT transistor. One of the

Generating true random bits of high quality at high data rates is usually viewed as a challenging task. To do so, physical sources of entropy with wide bandwidth are required which are able to provide truly random bits and not pseudorandom bits, as it is the case with deterministic algorithms and chaotic systems. In this work we demonstrate a reliable high-speed true random bit generator (TRBG)

In this work, a proposed circuit is implemented using tsmc 0.18um technology of area 16642 um2 with supply voltage equals 5V. A proposed implementation of a controllable Operational Transconductance Amplifier (OTA) slew rate for CMOS image sensor (CIS) is proposed. The slew rate is controlled by switching between various bias circuits for the OTA. The biasing circuit controls the value of OTA

In this short communication we analyze the impact of signal harmonics on the formation of the pinched hysteresis loop using a commercial memristor device. We show that by using only the fundamental frequency and the second harmonic components, extracted from the measured electrical current signal, a distortion-less pinched hysteresis loop is re-created. This loop is then used to simulate memristor

In this paper, we propose a MOS design of a second-order voltage-mode allpass filter to be used as a time delay cell. The proposed filter is based on a single transistor, three resistors and two energy storage elements and was designed in a 65nm CMOS technology. Post-layout simulations demonstrate a group delay of approximately 13ps across a 30GHz bandwidth, while only consuming 809.7μW from a 1-V

This paper is concerned with the generalization of continuous-time 3rd order low-pass filters to the fractional order domain. Three fractional-order capacitors of the same order α are to be considered in the process of filter design. A complete mathematical analysis of the 3rd order fractional low-pass filter is given with stability constraints taken into consideration. Finally, several low-pass

A novel topology for simultaneous emulation of fractional-order capacitors and inductors is presented in this paper. In particular, only one control terminal is used in order to select the type of the element as well as its fractional order. This is achieved through an appropriate fitting of the expressions of the intermediate bias currents, in such a way that, eventually, only the adjustment of