A novel low dropout (LDO) voltage regulator compensation technique is demonstrated. A parallel feedback path is used to insert a zero at approximately three times the output pole. The parallel feedback consists of passive elements only and occupies small area. The proposed technique completely eliminates the output pole at different load conditions and results in high LDO bandwidth, which achieves

This paper represents a new self timed signaling technique for low power SerDes transceiver. A three level coding technique enables extracting the clock from the data using simple phase detector rather than using complex power hungry blocks such as Clock Data Recovery (CDR) or a Phase Locked Loop (PLL). This SerDes transceiver was implemented using 90nm TSMC technology. The transmitter serializes

A novel double-bound hysteretic regulation scheme to control multi-phase interleaved Switched-Capacitor DC-DC converters is presented. The control scheme adjusts the number of interleaved phases with the SC converter's switching frequency to significantly reduce the required operating frequency of the control comparator, enabling the practical application of hysteretic control with large number of

As on-chip integration increases, the thermal distribution becomes spatially non-uniform and varies based on the power dissipation. In this paper, we introduce a temperature-aware task-mapping algorithm to prevent hotspots and achieve a highly uniform thermal distribution using adaptive multi-threshold values. The algorithm monitors the temperature of the cores, swaps tasks when the temperature of

To understand the physical process involved in film evaporation, a new numerical model is created using coupled quadratic finite element formulation of the conservation equations. The heat transport equation is solved in the three different phases (solid, liquid and vapor) while the Navier-Stokes equation are solved in the two fluids. The gradient discontinuity at the liquid vapor interface

A simple temperature sensor in Bi-CMOS technology is proposed for applications with low frequency temperature variations in addition to a complete analysis of each block in the system. Most CMOS temperature sensors are based on the temperature characteristics of parasitic bipolar transistors. Two important factors need to be met in the design of the sensor: the first is the accuracy of the sensor

A novel digital comparator topology is presented. The proposed digital comparator cell uses transistors' ratio to program a fixed comparison level. A double-bound hysteretic control comparator, for DC-DC converters, is built using the proposed digital comparator cell. The hysteretic-band width variation, due to process effects, decreases with increased preamplifier stage gain and constitutes a

A new clock distribution technique is introduced in this paper. The technique avoids repeaters completely and distributes the clock directly on the passive interconnect network. The wires can be highly lossy, yet the clock is delivered with a very good shape and eye. The technique uses the characteristics of the interconnect to attenuate all frequency components equally. The resulting clock at the

[No abstract available]

A major portion of the power consumed in today's systems is due to the clock distribution network. Solutions attempted to reduce clocking power result in low efficiency systems or systems with high complexity control schemes. In this work, a low power clock generator is introduced that can reduce switching power of the clock by almost 75%. This circuit uses the charge recycling concept to achieve